1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, for example, a read circuit system of a magnetic random access memory.
2. Description of the Related Art
As shown in FIG. 18, the magnetic random access memory cell is composed of a MTJ (Magnetic Tunnel Junction) element MTJ, and a select transistor Tr. The select transistor Tr has one terminal connected with the MTJ element and the other terminal connected with a ground potential line. The MTJ element has a stacked structure comprising two ferromagnetic layers and an insulating layer interposed between them, and records information using magnetic resistance changes by the spin polarization tunnel effect. Write to the MTJ element MTJ is carried out in the following manner. Bit line BL and write word line WWL, which are mutually orthogonal using the MTJ element MTJ as the intersecting point, change the relative spin direction of two ferromagnetic layers by the combined magnetic field. The gate of the select transistor Tr is connected with a read word line RWL for selecting the cell.
FIG. 19 is a view showing the configuration of principal parts of a conventional MRAM. The intersecting points of bit lines BL0 to BL3, RBL0, RBL1 and word lines WL0 to WL3 are each provided with a cell. In these cells, cells surrounded by a broken line are reference cells, and others are memory cells. A current conveyor CC converts the read potential read from memory cells MC and the reference potential read from reference cells RMC for generating reference potential into voltage. Thereafter, a sense amplifier SA compares and amplifies two voltages.
A reference potential read bus RDB is connected with two read gate transistors RQ. This is based on the following reason. Information (data) “0” and “1” stored in the reference cells RMC connected with read gate transistors are combined, thereby generating a binary intermediate reference potential. On the other hand, a read data bus DB is connected with some read gate transistors in accordance with the memory capacity. The number (total gate width) differs from the read gate transistor RQ. Thus, the total amount of PN junction leak current and channel leak current of these transistors Q and RQ, that is, CR time constant is different between read data buses DB and RDB. Accordingly, the voltage conversion speed of the current conveyor CC is different between read data buses DB and RDB. In particular, sense amplification is not normally carried out in the initial stage of the sense amplification, and thereby, there is a possibility that erroneous output Vout is outputted. As a result, read margin reduces.